div.hier_info

div的verilog开发程序

|div
q <= touch:inst4.q
reset => touch:inst4.reset
clk => touch:inst4.clk
out2 <= <GND>
out4 <= <GND>
out8 <= <GND>
out16 <= <GND>


|div|touch:inst4
reset => a[0].ACLR
reset => a[1].ACLR
reset => a[2].ACLR
reset => a[3].ACLR
reset => q~reg0.ENA
clk => q~reg0.CLK
clk => a[0].CLK
clk => a[1].CLK
clk => a[2].CLK
clk => a[3].CLK
q <= q~reg0.DB_MAX_OUTPUT_PORT_TYPE
div[0] <= a[0].DB_MAX_OUTPUT_PORT_TYPE
div[1] <= a[1].DB_MAX_OUTPUT_PORT_TYPE
div[2] <= a[2].DB_MAX_OUTPUT_PORT_TYPE
div[3] <= a[3].DB_MAX_OUTPUT_PORT_TYPE


|div|div2_4_8_16:inst5
a[0] => out2.DATAIN
a[1] => out4.DATAIN
a[2] => out8.DATAIN
a[3] => out16.DATAIN
out2 <= a[0].DB_MAX_OUTPUT_PORT_TYPE
out4 <= a[1].DB_MAX_OUTPUT_PORT_TYPE
out8 <= a[2].DB_MAX_OUTPUT_PORT_TYPE
out16 <= a[3].DB_MAX_OUTPUT_PORT_TYPE