hdb3.vhd

来自「hDB3的编解码模块 是在maxplusII 下验证过的 并且下到片子中都正」· VHDL 代码 · 共 36 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity hdb3 is
port(reset,clk,datain:in std_logic;
     dout: out std_logic_vector(1 downto 0));
end;

architecture rtl of hdb3 is
component hdb3a is
port(reset,clk,datain: in std_logic;
     dout: out std_logic_vector(1 downto 0));
end component;

component hdb is
port(reset,clk:in std_logic;
     datain: in std_logic_vector(1 downto 0);
     dout: out std_logic_vector(1 downto 0));
end component;

component hdb3c is
port(reset,clk: in std_logic;
     datain: in std_logic_vector(1 downto 0);
     dout: out std_logic_vector(1 downto 0));
end component;
signal d1,d2:std_logic_vector(1 downto 0);
begin
A: hdb3a port map(reset,clk,datain,d1);
B: hdb port map(reset,clk,d1,d2);
C: hdb3c port map(reset,clk,d2,dout);
end;