代码搜索:combinatorial
找到约 224 项符合「combinatorial」的源代码
代码结果 224
www.eeworm.com/read/341841/12058269
bgn clocktop.bgn
Release 6.1i - Bitgen G.23
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Loading device database for application Bitgen from file "clocktop.ncd".
"clocktop" is an NCD, version 2.38, d
www.eeworm.com/read/341841/12058299
bgn clockcore.bgn
Release 6.1i - Bitgen G.23
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Loading device database for application Bitgen from file "clockcore.ncd".
"clockcore" is an NCD, version 2.38,
www.eeworm.com/read/341841/12058599
drc clocktop.drc
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net clockkernel_mclkbuf
is sourced by a combinatorial pin. This is not good design practice. Use the
CE pin to control the loading of dat
www.eeworm.com/read/152187/12133523
abl demo331.abl
module DEMO331
title 'Cypress 331 example 12 Sep 1990'
" Feedback register node numbers.
" Pin number 15 16 17 18 19 20 23 24 25 26 27 28
" Feedback Node 143 144 145
www.eeworm.com/read/250077/12435589
drc szz.drc
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net _n0055 is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the fl
www.eeworm.com/read/336516/12440325
abl demo331.abl
module DEMO331
title 'Cypress 331 example 12 Sep 1990'
" Feedback register node numbers.
" Pin number 15 16 17 18 19 20 23 24 25 26 27 28
" Feedback Node 143 144 145
www.eeworm.com/read/219674/14870829
bgn top.bgn
Release 6.2i - Bitgen G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
Loading device database for application Bitgen from file "top.ncd".
"top" is an NCD, version 2.38, device xc2s
www.eeworm.com/read/219674/14871058
drc top.drc
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net U3_S1 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the fli
www.eeworm.com/read/214502/15098359
drc song.drc
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net carry is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the fli
www.eeworm.com/read/210234/15203124
drc pingche.drc
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net XLXN_25 is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the f