📄 szz.drc
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WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net _n0055 is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.DRC detected 0 errors and 1 warnings.⌨️ 快捷键说明
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