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来自「本代码介绍了使用VHDL开发FPGA的一般流程」· DRC 代码 · 共 29 行

WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net U3_S1 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net U3_S2 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net U3_S3 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net U3_S4 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net U3_S5 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net U3_carry is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net LOAD is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net U1_clk is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net CP is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
DRC detected 0 errors and 9 warnings.