代码搜索：adder
找到约 6,792 项符合「adder」的源代码
代码结果 6,792
www.eeworm.com/read/138605/13228640
vhd bcd3.vhd
--bcd3.vhd 3 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd3 is
port(
a : in std_logic_vector(11 downto 0);--砆
www.eeworm.com/read/310741/13644722
vhd bcd_add_sub.vhd
--bcd_add_sub.vhd 3 digits bcd adder/subtractor with start and done
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd_add_sub is
port(
clock : in std_logic ;--
www.eeworm.com/read/310741/13644749
vhd bcd3.vhd
--bcd3.vhd 3 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd3 is
port(
a : in std_logic_vector(11 downto 0);--砆
www.eeworm.com/read/306208/13749257
vhd bcd_add_sub.vhd
--bcd_add_sub.vhd 3 digits bcd adder/subtractor with start and done
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd_add_sub is
port(
clock : in std_logic ;--
www.eeworm.com/read/306208/13749283
vhd bcd3.vhd
--bcd3.vhd 3 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd3 is
port(
a : in std_logic_vector(11 downto 0);--砆
www.eeworm.com/read/301035/13868679
hif dds_vhdl.hif
Version 4.1 Build 181 06/29/2004 SJ Full Version
31
OFF
OFF
OFF
OFF
0
# entity
ADDER32B
# architecture
A:behav
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_fi
www.eeworm.com/read/264079/11330441
v c.v
module test_adder(out,in,m,Ti,r);
output[3:1] out;
reg[3:1] out;
wire check;
input [4:1] in;
wire [4:1] in;
output m;
integer m;
output r;
real r;
integer n;
time nTi
www.eeworm.com/read/259067/11823598
prj addere.prj
#-- Synplicity, Inc.
#-- Version 7.7.1
#-- Project file E:\QProj\AdderE\AdderE.prj
#-- Written on Mon May 01 16:07:01 2006
#add_file options
add_file -vhdl -lib work "Full_Adder.vhd"
ad
www.eeworm.com/read/13816/283928
vhd bcd_add_sub.vhd
--bcd_add_sub.vhd 3 digits bcd adder/subtractor with start and done
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd_add_sub is
port(
clock : in std_logic ;--
www.eeworm.com/read/13816/283955
vhd bcd3.vhd
--bcd3.vhd 3 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd3 is
port(
a : in std_logic_vector(11 downto 0);--砆