dds_vhdl.hif

这个是相当不错的EDA编程

Version 4.1 Build 181 06/29/2004 SJ Full Version
31
OFF
OFF
OFF
OFF
0
# entity
ADDER32B
# architecture
A:behav
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
adder32b.vhd
1089378682
4
# storage
db|dds_vhdl.(1).cnf
db|dds_vhdl.(1).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
REG32B
# architecture
A:behav
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
reg32b.vhd
1089378488
4
# storage
db|dds_vhdl.(2).cnf
db|dds_vhdl.(2).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
altsyncram_63p
# case_insensitive
# source_file
db|altsyncram_63p.tdf
1112684792
6
# storage
db|dds_vhdl.(5).cnf
db|dds_vhdl.(5).cnf
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
}
# memory_file {
.|data|LUT10X10.mif
1089429428
}
# end
# entity
ADDER10B
# architecture
A:behav
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
adder10b.vhd
1089432724
4
# storage
db|dds_vhdl.(6).cnf
db|dds_vhdl.(6).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
REG10B
# architecture
A:behav
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
reg10b.vhd
1089432902
4
# storage
db|dds_vhdl.(7).cnf
db|dds_vhdl.(7).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
SIN_ROM
# architecture
A:SYN
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
sin_rom.vhd
1118222178
4
# storage
db|dds_vhdl.(3).cnf
db|dds_vhdl.(3).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
altsyncram_gmu
# case_insensitive
# source_file
db|altsyncram_gmu.tdf
1118222194
6
# storage
db|dds_vhdl.(8).cnf
db|dds_vhdl.(8).cnf
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
}
# end
# entity
altsyncram_8kc2
# case_insensitive
# source_file
db|altsyncram_8kc2.tdf
1118222194
6
# storage
db|dds_vhdl.(9).cnf
db|dds_vhdl.(9).cnf
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
address_b7
address_b8
address_b9
clock0
clock1
data_b0
data_b1
data_b2
data_b3
data_b4
data_b5
data_b6
data_b7
data_b8
data_b9
wren_b
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
q_b8
q_b9
}
# memory_file {
DATA|LUT10X10.MIF
1089429428
}
# end
# entity
decode_9ie
# case_insensitive
# source_file
db|decode_9ie.tdf
1118222198
6
# storage
db|dds_vhdl.(16).cnf
db|dds_vhdl.(16).cnf
# used_port {
aclr
clken
clock
data0
data1
data2
enable
eq0
eq1
eq2
eq3
eq4
eq5
eq6
eq7
}
# end
# entity
cntr_kv8
# case_insensitive
# source_file
db|cntr_kv8.tdf
1118222200
6
# storage
db|dds_vhdl.(23).cnf
db|dds_vhdl.(23).cnf
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
data8
data9
clock
clk_en
aclr
sload
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
}
# end
# entity
cntr_pd8
# case_insensitive
# source_file
db|cntr_pd8.tdf
1118222200
6
# storage
db|dds_vhdl.(25).cnf
db|dds_vhdl.(25).cnf
# used_port {
clock
cnt_en
aclr
sclr
q0
q1
q2
q3
}
# end
# entity
cntr_mo8
# case_insensitive
# source_file
db|cntr_mo8.tdf
1118222546
6
# storage
db|dds_vhdl.(39).cnf
db|dds_vhdl.(39).cnf
# used_port {
clock
clk_en
aset
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
}
# end
# entity
cntr_e29
# case_insensitive
# source_file
db|cntr_e29.tdf
1118222546
6
# storage
db|dds_vhdl.(42).cnf
db|dds_vhdl.(42).cnf
# used_port {
clock
clk_en
cnt_en
aclr
sclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
}
# end
# entity
cntr_nt9
# case_insensitive
# source_file
db|cntr_nt9.tdf
1118222548
6
# storage
db|dds_vhdl.(56).cnf
db|dds_vhdl.(56).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
cout
}
# end
# entity
cntr_hv7
# case_insensitive
# source_file
db|cntr_hv7.tdf
1118222550
6
# storage
db|dds_vhdl.(62).cnf
db|dds_vhdl.(62).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
q5
}
# end
# entity
cntr_dn7
# case_insensitive
# source_file
db|cntr_dn7.tdf
1118222550
6
# storage
db|dds_vhdl.(64).cnf
db|dds_vhdl.(64).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
}
# end
# entity
cntr_en8
# case_insensitive
# source_file
db|cntr_en8.tdf
1118222654
6
# storage
db|dds_vhdl.(80).cnf
db|dds_vhdl.(80).cnf
# used_port {
clock
clk_en
aset
q0
q1
q2
q3
q4
q5
q6
q7
q8
}
# end
# entity
cntr_619
# case_insensitive
# source_file
db|cntr_619.tdf
1118222656
6
# storage
db|dds_vhdl.(83).cnf
db|dds_vhdl.(83).cnf
# used_port {
clock
clk_en
cnt_en
aclr
sclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
}
# end
# entity
cntr_0r9
# case_insensitive
# source_file
db|cntr_0r9.tdf
1118222658
6
# storage
db|dds_vhdl.(91).cnf
db|dds_vhdl.(91).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
cout
}
# end
# entity
cntr_mk7
# case_insensitive
# source_file
db|cntr_mk7.tdf
1118222660
6
# storage
db|dds_vhdl.(97).cnf
db|dds_vhdl.(97).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
}
# end
# entity
altsyncram
# case_insensitive
# source_file
..|..|..|..|..|altera|quartus41|libraries|megafunctions|altsyncram.tdf
1088009418
6
# storage
db|dds_vhdl.(4).cnf
db|dds_vhdl.(4).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
10
PARAMETER_DEC
USR
WIDTHAD_A
10
PARAMETER_DEC
USR
NUMWORDS_A
1024
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
F:/EP1C3_13_10_PHAS/DATA/LUT10X10.MIF
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_gmu
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
}
# include_file {
..|..|..|..|..|altera|quartus41|libraries|megafunctions|stratix_ram_block.inc
1081479498
..|..|..|..|..|altera|quartus41|libraries|megafunctions|lpm_mux.inc
1081478758
..|..|..|..|..|altera|quartus41|libraries|megafunctions|lpm_decode.inc
1081478592
..|..|..|..|..|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
..|..|..|..|..|altera|quartus41|libraries|megafunctions|altsyncram.inc
1081477654
..|..|..|..|..|altera|quartus41|libraries|megafunctions|a_rdenreg.inc
1081476578
..|..|..|..|..|altera|quartus41|libraries|megafunctions|altrom.inc
1081477590
..|..|..|..|..|altera|quartus41|libraries|megafunctions|altram.inc
1081477560
..|..|..|..|..|altera|quartus41|libraries|megafunctions|altdpram.inc
1081477328
..|..|..|..|..|altera|quartus41|libraries|megafunctions|altqpram.inc
1081477546
}
# end
# entity
sld_mod_ram_rom
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|..|..|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
4
# storage
db|dds_vhdl.(10).cnf
db|dds_vhdl.(10).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# user_parameter {
sld_node_info
1601024
PARAMETER_DEC
DEF
sld_ip_version
0
PARAMETER_DEC
DEF
sld_ip_minor_version
0
PARAMETER_DEC
DEF
sld_common_ip_version
0
PARAMETER_DEC