addere.prj

altera Quartus II modelSim 自動模擬搭配

#-- Synplicity, Inc.
#-- Version 7.7.1     
#-- Project file E:\QProj\AdderE\AdderE.prj
#-- Written on Mon May 01 16:07:01 2006


#add_file options
add_file -vhdl -lib work "Full_Adder.vhd"
add_file -vhdl -lib work "AdderE.vhd"


#implementation: "rev_1"
impl -add rev_1

#device options
set_option -technology CYCLONE
set_option -part EP1C6
set_option -package FC256
set_option -speed_grade -8

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler 0
set_option -resource_sharing 0
set_option -use_fsm_explorer 0
set_option -top_module "AdderE"

#map options
set_option -frequency auto
set_option -fanout_limit 30
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 1
set_option -fixgatedclocks 0
set_option -verification_mode 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_1/AdderE.vqm"

#implementation attributes
set_option -vlog_std v2001
set_option -synthesis_onoff_pragma 0
impl -active "rev_1"