addere.vhd

来自「altera Quartus II modelSim 自動模擬搭配」· VHDL 代码 · 共 32 行

-- File Name: AdderE.vhd
entity AdderE is
	port(
			A,B	:	in	BIT_VECTOR(7 downto 0);
			CIN	:	in	BIT;
			COUT	:	out	BIT;
			SUM	:	out BIT_VECTOR(7 downto 0)
		);
end entity AdderE;

architecture syn of AdderE is
component Full_Adder
	port(
			X,Y,CIN	:	in	BIT;
			COUT	:	out BIT;
			SUM		:	out	BIT
		);
end component Full_Adder;
	signal C	:	BIT_VECTOR(7 downto 0); 
begin
	Stages : for i in 7 downto 0 generate
		LowBit	: if	i = 0 generate
			FA:Full_Adder port map (A(0),B(0),CIN,C(0),SUM(0));
 	    end generate;
		OtherBits : if i /= 0 generate
			FA:Full_Adder port map (A(i),B(i),C(i-1),C(i),SUM(i));
		end generate;
	end generate;
	COUT <= C(7);
end architecture syn;