full_adder.vhd

来自「altera Quartus II modelSim 自動模擬搭配」· VHDL 代码 · 共 19 行

-- FileName: Full_Adder.vhd
entity Full_Adder is
	port(
			X,Y,CIN	:	in	BIT;
			COUT	:	out BIT;
			SUM		:	out	BIT
		);
end entity Full_Adder;

architecture syn of Full_Adder is
	signal temp1,temp2 : BIT;
begin
	temp1 <= X xor Y;
	temp2 <= temp1 and CIN;
	SUM <= temp1 xor CIN;
	COUT <= temp2 OR (X and Y);
	
end architecture syn;