c.v

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module test_adder(out,in,m,Ti,r);
   output[3:1] out;
   reg[3:1] out;
   wire check;
   input [4:1] in;
   wire [4:1] in;
   output m;
   integer m;
   output r;
   real r;
   integer n;
   time  nTime;
   output Ti;
   realtime Ti;
   null_module test(nTime,n);
   carry (check,nTime,n,in);
endmodule
module null_module(out1,out2);
input [63:0] out1;
input [31:0]out2;
endmodule
primitive carry(carryOut,carryIn,aIn,bIn);
    output carryOut;
    input  carryIn,
           aIn,bIn;
    
    table
  // carryIn  aIn  bIn    carryOut
       0       0   0   :    0;
	endtable 
endprimitive