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Verilog 的代码
sum_control.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
main.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Qua
sum_control.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity pn_encode is
port(
data_source : in vl_logic;
init : in vl_logic;
clk_pn : in vl_logic
cpld_for_lcd.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity Ser_Par_Conv_32 is
generic(
S_idle : integer := 0;
S_1 : integer := 1
);
port(
Data_out
i2c.npl
JDF G
// Created by Project Navigator ver 1.0
PROJECT I2C
DESIGN i2c
DEVFAM spartan2e
DEVFAMTIME 0
DEVICE xc2s50e
DEVICETIME 0
DEVPKG tq144
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLE
i2c.gfl
# XST (Creating Lso File) :
i2c_master_top.lso
# Check Syntax
i2c_master_top.stx
# XST (Creating Lso File) :
i2c_master_bit_ctrl.lso
# Check Syntax
i2c_master_bit_ctrl.stx
# xst flow : RunXS
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ddr_control_interface is
port(
clk : in vl_logic;
reset_n : in vl_logic;
cmd : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity spu is
port(
decisions_s1 : in vl_logic_vector(3 downto 0);
decoded_column_s1: out vl_logic_vector(3 downto 0);