_primary.vhd

来自「同步及异步时序电路fifo源程序及其测试程序.rar - fifo源程序」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity Ser_Par_Conv_32 is
    generic(
        S_idle          : integer := 0;
        S_1             : integer := 1
    );
    port(
        Data_out        : out    vl_logic_vector(31 downto 0);
        write           : out    vl_logic;
        Data_in         : in     vl_logic;
        En              : in     vl_logic;
        clk             : in     vl_logic;
        rst             : in     vl_logic
    );
end Ser_Par_Conv_32;