_primary.vhd

来自「系数为4的扰码生成器」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity pn_encode is
    port(
        data_source     : in     vl_logic;
        init            : in     vl_logic;
        clk_pn          : in     vl_logic;
        reset_pn        : in     vl_logic;
        flag_tra        : out    vl_logic;
        pn_out          : out    vl_logic
    );
end pn_encode;