_primary.vhd

viterbi decoder , use verilog HDL language.

library verilog;
use verilog.vl_types.all;
entity spu is
    port(
        decisions_s1    : in     vl_logic_vector(3 downto 0);
        decoded_column_s1: out    vl_logic_vector(3 downto 0);
        phi1            : in     vl_logic;
        phi2            : in     vl_logic
    );
end spu;