_primary.vhd

Sdr SDRAM控制器参考设计,很好的

library verilog;
use verilog.vl_types.all;
entity ddr_control_interface is
    port(
        clk             : in     vl_logic;
        reset_n         : in     vl_logic;
        cmd             : in     vl_logic_vector(2 downto 0);
        addr            : in     vl_logic_vector(21 downto 0);
        ref_ack         : in     vl_logic;
        cm_ack          : in     vl_logic;
        nop             : out    vl_logic;
        reada           : out    vl_logic;
        writea          : out    vl_logic;
        refresh         : out    vl_logic;
        precharge       : out    vl_logic;
        load_mode       : out    vl_logic;
        saddr           : out    vl_logic_vector(21 downto 0);
        sc_cl           : out    vl_logic_vector(1 downto 0);
        sc_rc           : out    vl_logic_vector(1 downto 0);
        sc_rrd          : out    vl_logic_vector(3 downto 0);
        sc_pm           : out    vl_logic;
        sc_bl           : out    vl_logic_vector(3 downto 0);
        ref_req         : out    vl_logic;
        cmd_ack         : out    vl_logic
    );
end ddr_control_interface;