代码搜索结果
找到约 10,000 项符合
Verilog 的代码
vga.fit.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
内容简介.txt
本书简要介绍了<mark>Verilog</mark>硬件描述语言的基础知识，包括语言的基本内容和基本结构 ，以及利用该语言在各种层次上对数字系统的建模方法。书中列举了大量实例，帮助读者掌握语言本身和建模方法，对实际数字系统设计也很有帮助。本书是<mark>Verilog</mark> HDL的初级读本，适用于作为计算机、电子、电气及自控等专业相关课程的教材，也可供有关的科研人员作为参考书。
...
i2c_altera.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity modulator is
port(
gclk : in vl_logic;
ex_pm : in vl_logic;
ex_bds : in vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity dcmclk is
port(
CLKIN_IN : in vl_logic;
CLKIN_IBUFG_OUT : out vl_logic;
CLK0_OUT : out vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity sel_tmp2 is
port(
sel_imm : in vl_logic;
ram_out : in vl_logic_vector(7 downto 0);
literalk
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stack is
port(
clk4 : in vl_logic;
pc_addr : in vl_logic_vector(10 downto 0);
stack_call :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity uart_tx is
port(
rst : in vl_logic;
clk16x : in vl_logic;
din : in vl_logic_v
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity uart is
port(
wr : in vl_logic;
rst : in vl_logic;
clk : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ADDSUB_16_0 is
generic(
word_in_size : integer := 16
);
port(
add_sub : in vl_logic;
dataa