_primary.vhd

来自「此代码可用modelsim进行仿真」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity stack is
    port(
        clk4            : in     vl_logic;
        pc_addr         : in     vl_logic_vector(10 downto 0);
        stack_call      : in     vl_logic;
        stack_retlw     : in     vl_logic;
        stack1          : out    vl_logic_vector(10 downto 0)
    );
end stack;