_primary.vhd

来自「复乘法器的FPGA实现」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity ADDSUB_16_0 is
    generic(
        word_in_size    : integer := 16
    );
    port(
        add_sub         : in     vl_logic;
        dataa           : in     vl_logic_vector;
        datab           : in     vl_logic_vector;
        result          : out    vl_logic_vector
    );
end ADDSUB_16_0;