_primary.vhd

来自「运用FPGA控制AD9957的操作」· VHDL 代码 · 共 31 行

library verilog;
use verilog.vl_types.all;
entity modulator is
    port(
        gclk            : in     vl_logic;
        ex_pm           : in     vl_logic;
        ex_bds          : in     vl_logic;
        ex_opt          : in     vl_logic;
        ex_pms          : in     vl_logic;
        ex_ppt          : in     vl_logic;
        ex_opt0         : in     vl_logic;
        ex_opt1         : in     vl_logic;
        ex_clk          : in     vl_logic;
        sdo             : in     vl_logic;
        io_reset        : out    vl_logic;
        pdclk           : out    vl_logic;
        ncs             : out    vl_logic;
        io_update       : out    vl_logic;
        tx_en           : out    vl_logic;
        rt              : out    vl_logic;
        osk             : out    vl_logic;
        sclk            : out    vl_logic;
        sdio            : out    vl_logic;
        pwr_dwn         : out    vl_logic;
        tp              : in     vl_logic_vector(7 downto 0);
        profile         : out    vl_logic_vector(2 downto 0);
        tp_out          : out    vl_logic_vector(5 downto 0);
        dout            : out    vl_logic_vector(17 downto 0)
    );
end modulator;