_primary.vhd

实现FPGA与PC机的串口通信功能

library verilog;
use verilog.vl_types.all;
entity uart is
    port(
        wr              : in     vl_logic;
        rst             : in     vl_logic;
        clk             : in     vl_logic;
        rd              : in     vl_logic;
        rxd             : in     vl_logic;
        data_in         : in     vl_logic_vector(7 downto 0);
        parity_def      : in     vl_logic;
        int             : out    vl_logic;
        txd             : out    vl_logic;
        dat_rdy         : out    vl_logic;
        tbre            : out    vl_logic;
        framing_error   : out    vl_logic;
        parity_error    : out    vl_logic;
        data_out        : out    vl_logic_vector(7 downto 0)
    );
end uart;