_primary.vhd

来自「实现FPGA与PC机的串口通信功能」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity uart_tx is
    port(
        rst             : in     vl_logic;
        clk16x          : in     vl_logic;
        din             : in     vl_logic_vector(7 downto 0);
        wr              : in     vl_logic;
        parity_def      : in     vl_logic;
        tbre            : out    vl_logic;
        sdo             : out    vl_logic
    );
end uart_tx;