代码搜索结果

m255 cModel Technology dE:\刘韬\MY_WORK\FPGA\程序\I2C vglbl I;3bdO6U;R_i?oXm0zZ=6m3 V]6_PH00iDgcD`AVz9`gA:0 w1059855545 FC:/Program Files/Xilinx/verilog/src/glbl.v L0 5 OE;L;5.7e;17 r1 31 vi2c_slave_model

# Copyright (C) 1991-2004 Altera Corporation # Any megafunction design, and related netlist (encrypted or decrypted), # support information, device programming or simulation file, and any oth

set tool_name "ModelSim-Altera (Verilog)" set corner_file_list { {{"Slow Model"} {kkd.vo kkd_v.sdo}} }

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any

Version 7.2 Build 151 09/26/2007 SJ Web Edition 35 2631 OFF OFF OFF OFF ON ON ON FV_OFF Level2 0 0 VRSM_ON VHSM_ON 0 -- Start Partition -- -- End Partition -- -- Start Library Paths

License checkout: synplifypro Starting: d:\EDA\Synplicity\fpga_81\bin\mbin\synplify.exe Install: d:\EDA\Synplicity\fpga_81 Date: Fri Mar 27 16:35:33 2009 Version: 8.1 Versio

m255 cModel Technology dE:\刘韬\MY_WORK\FPGA\程序\I2C vglbl I;3bdO6U;R_i?oXm0zZ=6m3 V]6_PH00iDgcD`AVz9`gA:0 w1059855545 FC:/Program Files/Xilinx/verilog/src/glbl.v L0 5 OE;L;5.7e;17 r1 31 vi2c_slave_model

//********************************************************* // IEEE STD 1364-1995 Verilog file: iir.v // Author-EMAIL: Uwe.Meyer-Baese@ieee.org //***************************************************