core_1c6.qsf

运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形.

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		core_1c6_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:30:51  MARCH 29, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION 5.1
set_global_assignment -name VERILOG_FILE fp_2.v
set_global_assignment -name VERILOG_FILE pipeline_add_64.v
set_global_assignment -name VERILOG_FILE data_ctl.v
set_global_assignment -name VERILOG_FILE bus_connect.v
set_global_assignment -name VERILOG_FILE scankey.v
set_global_assignment -name VERILOG_FILE asic74573.v
set_global_assignment -name VERILOG_FILE asic74138.v
set_global_assignment -name BDF_FILE core_1c6.bdf
set_global_assignment -name VERILOG_FILE RAM_ADDR.v
set_global_assignment -name VERILOG_FILE ScanKey_4_4.v

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_226 -to ALE
set_location_assignment PIN_199 -to P0[0]
set_location_assignment PIN_202 -to P0[1]
set_location_assignment PIN_205 -to P0[2]
set_location_assignment PIN_208 -to P0[3]
set_location_assignment PIN_215 -to P0[4]
set_location_assignment PIN_218 -to P0[5]
set_location_assignment PIN_221 -to P0[6]
set_location_assignment PIN_224 -to P0[7]
set_location_assignment PIN_239 -to P2[0]
set_location_assignment PIN_238 -to P2[1]
set_location_assignment PIN_237 -to P2[2]
set_location_assignment PIN_236 -to P2[3]
set_location_assignment PIN_235 -to P2[4]
set_location_assignment PIN_234 -to P2[5]
set_location_assignment PIN_233 -to P2[6]
set_location_assignment PIN_228 -to P2[7]
set_location_assignment PIN_195 -to CnD
set_location_assignment PIN_196 -to nLCD_CS
set_location_assignment PIN_197 -to nLCD_RD
set_location_assignment PIN_198 -to nLCD_WR
set_location_assignment PIN_223 -to nRD
set_location_assignment PIN_222 -to nWR
set_location_assignment PIN_194 -to lcd_data[0]
set_location_assignment PIN_193 -to lcd_data[1]
set_location_assignment PIN_188 -to lcd_data[2]
set_location_assignment PIN_187 -to lcd_data[3]
set_location_assignment PIN_186 -to lcd_data[4]
set_location_assignment PIN_185 -to lcd_data[5]
set_location_assignment PIN_184 -to lcd_data[6]
set_location_assignment PIN_183 -to lcd_data[7]
set_location_assignment PIN_182 -to FS
set_location_assignment PIN_225 -to EA
set_location_assignment PIN_217 -to INT1
set_location_assignment PIN_108 -to KC[0]
set_location_assignment PIN_107 -to KC[1]
set_location_assignment PIN_106 -to KC[2]
set_location_assignment PIN_113 -to KR[0]
set_location_assignment PIN_114 -to KR[1]
set_location_assignment PIN_115 -to KR[2]
set_location_assignment PIN_116 -to KR[3]
set_location_assignment PIN_117 -to KR[4]
set_location_assignment PIN_118 -to KR[5]
set_location_assignment PIN_105 -to KP[0]
set_location_assignment PIN_104 -to KP[1]
set_location_assignment PIN_103 -to KP[2]
set_location_assignment PIN_102 -to KP[3]
set_location_assignment PIN_101 -to KP[4]
set_location_assignment PIN_100 -to KP[5]
set_location_assignment PIN_94 -to LED[0]
set_location_assignment PIN_95 -to LED[1]
set_location_assignment PIN_96 -to LED[2]
set_location_assignment PIN_97 -to LED[3]
set_location_assignment PIN_98 -to LED[4]
set_location_assignment PIN_99 -to LED[5]
set_location_assignment PIN_28 -to CLK_40

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY core_1c6

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C6Q240C8
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT ON
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL

# Assembler Assignments
# =====================
set_global_assignment -name COMPRESSION_MODE ON
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1.0
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPC4
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE OFF
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"

# Simulator Assignments
# =====================
set_global_assignment -name GLITCH_INTERVAL "1 ns"

# Programmer Assignments
# ======================
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED OFF

# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE "D:\\altera\\quartus42\\project\\core_1c6\\stp2.stp"

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF

set_global_assignment -name VERILOG_FILE add18.v
set_global_assignment -name VERILOG_FILE asic4_16.v
set_global_assignment -name VERILOG_FILE Adr4_16.v
set_global_assignment -name VERILOG_FILE fp2.v
set_global_assignment -name VERILOG_FILE Tlc5510.v
set_global_assignment -name VERILOG_FILE count.v
set_location_assignment PIN_200 -to P1[0]
set_location_assignment PIN_201 -to P1[1]
set_location_assignment PIN_203 -to P1[2]
set_location_assignment PIN_204 -to P1[3]
set_location_assignment PIN_206 -to P1[4]
set_location_assignment PIN_207 -to P1[5]
set_location_assignment PIN_213 -to P1[6]
set_location_assignment PIN_214 -to P1[7]
set_location_assignment PIN_87 -to in1[0]
set_location_assignment PIN_93 -to in1[1]
set_location_assignment PIN_16 -to in1[2]
set_location_assignment PIN_14 -to in1[3]
set_location_assignment PIN_12 -to in1[4]
set_location_assignment PIN_8 -to in1[5]
set_location_assignment PIN_6 -to in1[6]
set_location_assignment PIN_4 -to in1[7]
set_location_assignment PIN_80 -to in2[0]
set_location_assignment PIN_78 -to in2[1]
set_location_assignment PIN_76 -to in2[2]
set_location_assignment PIN_74 -to in2[3]
set_location_assignment PIN_68 -to in2[4]
set_location_assignment PIN_66 -to in2[5]
set_location_assignment PIN_83 -to in2[6]
set_location_assignment PIN_85 -to in2[7]
set_location_assignment PIN_11 -to out11
set_location_assignment PIN_79 -to out79
set_location_assignment PIN_7 -to out7
set_location_assignment PIN_13 -to out13
set_location_assignment PIN_15 -to out15
set_location_assignment PIN_23 -to Fre17
set_location_assignment PIN_77 -to out0800[0]
set_location_assignment PIN_75 -to out0800[1]
set_location_assignment PIN_73 -to out0800[2]
set_location_assignment PIN_67 -to out0800[3]
set_location_assignment PIN_82 -to out0800[4]
set_location_assignment PIN_84 -to out0800[5]
set_location_assignment PIN_86 -to out0800[6]
set_location_assignment PIN_88 -to out0800[7]
set_location_assignment PIN_5 -to out5
set_global_assignment -name VERILOG_FILE div_100.v
set_global_assignment -name VERILOG_FILE "select2-1.v"
set_global_assignment -name VERILOG_FILE chufa.v
set_global_assignment -name VERILOG_FILE div_10.v
set_global_assignment -name VERILOG_FILE ce_gao.v