stdout.log

来自「实现FPGA与DSP之间通信的接口,利用DSP的标准EMIF接口」· LOG 代码 · 共 50 行

License checkout: synplifypro

Starting:    d:\EDA\Synplicity\fpga_81\bin\mbin\synplify.exe
Install:     d:\EDA\Synplicity\fpga_81
Date:        Fri Mar 27 16:35:33 2009
Version:     8.1

Version 8.1

Arguments:   -pro -batch -splash -launchmode EMIF_COM.prj -tcl EMIF_COM_map.tcl
ProductType: synplify_pro

License: synplifypro node-locked 
Running in Xilinx Mode



Running synthesis on EMIF_COM:EMIF_COM

log file: "E:\ISE_Prj\EMIF_COM\EMIF_COM.srr"


Running Verilog Compiler...

Verilog Compiler Completed


Verilog Compiler: 0 errors, 23 warnings, 1 note - from log file E:\ISE_Prj\EMIF_COM\EMIF_COM.srr


Total: 0 errors, 23 warnings, 1 note

Running SPARTAN2 Mapper...

Launching mapper in pro mode

SPARTAN2 Mapper Completed with warnings


SPARTAN2 Mapper: 0 errors, 29 warnings, 6 notes - from log file E:\ISE_Prj\EMIF_COM\EMIF_COM.srr


Total: 0 errors, 52 warnings, 7 notes

TCL script complete: "E:\ISE_Prj\EMIF_COM\EMIF_COM_map.tcl"

exit status=0