pwm.map.qmsg

FPGA下PWM的Verilog 源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 14 19:57:10 2007 " "Info: Processing started: Thu Jun 14 19:57:10 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off pwm -c pwm " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pwm -c pwm" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "pwm.v(388) " "Warning (10268): Verilog HDL information at pwm.v(388): Always Construct contains both blocking and non-blocking assignments" {  } { { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 388 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Warning" "WVRFX_VERI_IGNORED_ANONYMOUS_PORT" "pwm pwm.v(1) " "Warning (10238): Verilog Module Declaration warning at pwm.v(1): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"pwm\"" {  } { { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 1 0 0 } }  } 0 10238 "Verilog Module Declaration warning at %2!s!: ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"%1!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "pwm.v 1 1 " "Warning: Using design file pwm.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Info: Found entity 1: pwm" {  } { { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "pwm " "Info: Elaborating entity \"pwm\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 pwm.v(45) " "Warning (10230): Verilog HDL assignment warning at pwm.v(45): truncated value with size 32 to match size of target (10)" {  } { { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 45 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 pwm.v(48) " "Warning (10230): Verilog HDL assignment warning at pwm.v(48): truncated value with size 32 to match size of target (6)" {  } { { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 48 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 pwm.v(327) " "Warning (10230): Verilog HDL assignment warning at pwm.v(327): truncated value with size 32 to match size of target (11)" {  } { { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 327 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 pwm.v(339) " "Warning (10230): Verilog HDL assignment warning at pwm.v(339): truncated value with size 32 to match size of target (11)" {  } { { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 339 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 pwm.v(399) " "Warning (10230): Verilog HDL assignment warning at pwm.v(399): truncated value with size 32 to match size of target (6)" {  } { { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 399 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "flag_sin1 0 pwm.v(16) " "Warning (10030): Tied undriven net \"flag_sin1\" at pwm.v(16) to 0" {  } { { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 16 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "amp_sin1\[10\] data_in GND " "Warning: Reduced register \"amp_sin1\[10\]\" with stuck data_in port to stuck value GND" {  } { { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 308 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "amp_sin1\[9\] data_in GND " "Warning: Reduced register \"amp_sin1\[9\]\" with stuck data_in port to stuck value GND" {  } { { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 308 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "sys_cnt\[0\]~18 6 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: \"sys_cnt\[0\]~18\"" {  } { { "pwm.v" "sys_cnt\[0\]~18" { Text "E:/code/verilog/lai_PWM/pwm.v" 308 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:sys_cnt_rtl_0 " "Info: Elaborated megafunction instantiation \"lpm_counter:sys_cnt_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add4 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add4\"" {  } { { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 399 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus60/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}