jiaotongdeng.qsf

这程序是利用状态机来控制交通灯verilog码

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		jiaotongdeng_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C5Q208C8
set_global_assignment -name TOP_LEVEL_ENTITY jiaotongdeng
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:38:53  DECEMBER 17, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 8.1
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_global_assignment -name VERILOG_FILE jiaotongdeng.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name BDF_FILE Block1.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE jiaotongdeng.vwf
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE jiaotongdeng.vwf
set_global_assignment -name VERILOG_FILE int_div.v
set_global_assignment -name VERILOG_FILE int_div2.v
set_global_assignment -name VERILOG_FILE jiaotongdeng_con.v
set_global_assignment -name VERILOG_FILE seg_7.v
set_global_assignment -name BDF_FILE jiaotongdeng.bdf
set_location_assignment PIN_23 -to clock
set_location_assignment PIN_74 -to clr
set_location_assignment PIN_88 -to ra
set_location_assignment PIN_90 -to ya
set_location_assignment PIN_94 -to ga
set_location_assignment PIN_99 -to yb
set_location_assignment PIN_102 -to gb
set_location_assignment PIN_96 -to rb
set_location_assignment PIN_135 -to seg[0]
set_location_assignment PIN_141 -to seg[1]
set_location_assignment PIN_127 -to seg[2]
set_location_assignment PIN_115 -to seg[3]
set_location_assignment PIN_113 -to seg[4]
set_location_assignment PIN_138 -to seg[5]
set_location_assignment PIN_133 -to seg[6]
set_location_assignment PIN_117 -to seg[7]
set_location_assignment PIN_89 -to scan[0]
set_location_assignment PIN_92 -to scan[1]
set_location_assignment PIN_95 -to scan[2]
set_location_assignment PIN_97 -to scan[3]
set_location_assignment PIN_103 -to scan[5]
set_location_assignment PIN_101 -to scan[4]
set_location_assignment PIN_105 -to scan[6]
set_location_assignment PIN_110 -to scan[7]
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name MISC_FILE "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/jiaotongdeng.dpf"