代码搜索结果

library verilog; use verilog.vl_types.all; entity viterbi12_s is port( data_in0 : in vl_logic_vector(2 downto 0); data_in1 : in vl_logic_vector(2 downto 0);

library verilog; use verilog.vl_types.all; entity dcm165m is port( CLKIN_IN : in vl_logic; RST_IN : in vl_logic; CLKFX_OUT : out vl_logic;

library verilog; use verilog.vl_types.all; entity decode_BPSK_12 is port( clk : in vl_logic; code_clk_i : in vl_logic; code0_i3 : in vl_

library verilog; use verilog.vl_types.all; entity viterbi is port( data_in0 : in vl_logic_vector(2 downto 0); data_out : out vl_logic; rdy

library verilog; use verilog.vl_types.all; entity decode_BPSK_34 is port( clk : in vl_logic; code_clk_i : in vl_logic; code0_i3 : in vl_

m255 cModel Technology dE:\刘韬\MY_WORK\FPGA\程序\I2C vglbl I;3bdO6U;R_i?oXm0zZ=6m3 V]6_PH00iDgcD`AVz9`gA:0 w1059855545 FC:/Program Files/Xilinx/verilog/src/glbl.v L0 5 OE;L;5.7e;17 r1 31 vi2c_slave_model

m255 cModel Technology dE:\刘韬\MY_WORK\FPGA\程序\I2C vglbl I;3bdO6U;R_i?oXm0zZ=6m3 V]6_PH00iDgcD`AVz9`gA:0 w1059855545 FC:/Program Files/Xilinx/verilog/src/glbl.v L0 5 OE;L;5.7e;17 r1 31 vi2c_slave_model

library verilog; use verilog.vl_types.all; entity rom_altsyncram is port( aclr0 : in vl_logic; address_a : in vl_logic_vector(7 downto 0); clock0

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any

library verilog; use verilog.vl_types.all; entity config_dac is generic( IDLE : integer := 1; START : integer := 2; INSTRUCTION : integer := 4;