_primary.vhd

来自「采用匹配滤波」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity viterbi is
    port(
        data_in0        : in     vl_logic_vector(2 downto 0);
        data_out        : out    vl_logic;
        rdy             : out    vl_logic;
        aclr            : in     vl_logic;
        clk             : in     vl_logic
    );
end viterbi;