_primary.vhd

来自「FPGA中实现基于查找表方式（LUT）的DDS实现」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity rom_altsyncram is
    port(
        aclr0           : in     vl_logic;
        address_a       : in     vl_logic_vector(7 downto 0);
        clock0          : in     vl_logic;
        q_a             : out    vl_logic_vector(7 downto 0)
    );
end rom_altsyncram;