_primary.vhd

来自「FPGA中实现基于查找表方式（LUT）的DDS实现」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity dds is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        k               : in     vl_logic_vector(9 downto 0);
        initial_phase   : in     vl_logic_vector(9 downto 0);
        data_out        : out    vl_logic_vector(7 downto 0)
    );
end dds;