_primary.vhd

采用匹配滤波

library verilog;
use verilog.vl_types.all;
entity decode_BPSK_12 is
    port(
        clk             : in     vl_logic;
        code_clk_i      : in     vl_logic;
        code0_i3        : in     vl_logic_vector(2 downto 0);
        code1_i3        : in     vl_logic_vector(2 downto 0);
        reset           : in     vl_logic;
        frame_syn       : in     vl_logic;
        data_clk_o      : out    vl_logic;
        data0_o         : out    vl_logic;
        data1_o         : out    vl_logic;
        ceshi           : out    vl_logic_vector(15 downto 0);
        add_31          : in     vl_logic_vector(30 downto 0);
        qufan           : in     vl_logic;
        lost_syn        : out    vl_logic;
        decode_syn      : out    vl_logic
    );
end decode_BPSK_12;