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//********************************************************* // IEEE STD 1364-1995 Verilog file: lfsr6s3.v // Author-EMAIL: Uwe.Meyer-Baese@ieee.org //**********************************************

//********************************************************* // IEEE STD 1364-1995 Verilog file: lfsr6s3.v // Author-EMAIL: Uwe.Meyer-Baese@ieee.org //**********************************************

library verilog; use verilog.vl_types.all; entity half_clk is port( reset : in vl_logic; clk_in : in vl_logic; clk_out : out vl_logic

Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version 11 990 OFF OFF OFF OFF ON ON ON FV_OFF Level2 0 0 VRSM_ON VHSM_ON 0 -- Start Partition -- -- End Partition -- -- Star

library verilog; use verilog.vl_types.all; entity pram is generic( word_depth : integer := 2048 ); port( clk : in vl_logic; address : i

library verilog; use verilog.vl_types.all; entity dram is generic( word_depth : integer := 70 ); port( clk : in vl_logic; address : in

library verilog; use verilog.vl_types.all; entity clearable_register is port( clk : in vl_logic; din : in vl_logic_vector(31 downto 0); dout

library verilog; use verilog.vl_types.all; entity plain_register is port( clk : in vl_logic; din : in vl_logic_vector(31 downto 0); dout

library verilog; use verilog.vl_types.all; entity clearable_register is port( clk : in vl_logic; din : in vl_logic_vector(31 downto 0); dout

library verilog; use verilog.vl_types.all; entity adder6 is port( s : out vl_logic_vector(5 downto 0); co : out vl_logic; a :