_primary.vhd

来自「用Verilog 编写的8位risc cpu」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity pram is
    generic(
        word_depth      : integer := 2048
    );
    port(
        clk             : in     vl_logic;
        address         : in     vl_logic_vector(10 downto 0);
        we              : in     vl_logic;
        din             : in     vl_logic_vector(11 downto 0);
        dout            : out    vl_logic_vector(11 downto 0)
    );
end pram;