_primary.vhd

来自「ARM10 INSTALALTION GUIDE」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity clearable_register is
    port(
        clk             : in     vl_logic;
        din             : in     vl_logic_vector(31 downto 0);
        dout            : out    vl_logic_vector(31 downto 0);
        clr             : in     vl_logic;
        ld              : in     vl_logic
    );
end clearable_register;