_primary.vhd

来自「ARM10 INSTALALTION GUIDE」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity adder6 is
    port(
        s               : out    vl_logic_vector(5 downto 0);
        co              : out    vl_logic;
        a               : in     vl_logic_vector(5 downto 0);
        b               : in     vl_logic_vector(5 downto 0);
        cin             : in     vl_logic;
        v               : out    vl_logic
    );
end adder6;