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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity add_ahead is
port(
sum : out vl_logic_vector(7 downto 0);
cout : out vl_logic;
a
lfsr6s3.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr6s3.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**********************************************
lfsr6s3.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr6s3.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**********************************************
lfsr6s3.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr6s3.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**********************************************
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity CMULTIPLEX is
generic(
word_in_size : integer := 16
);
port(
clk : in vl_logic;
clkena
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ADDSUB is
port(
add_sub : in vl_logic;
dataa : in vl_logic_vector(15 downto 0);
datab
exemplar.his
#
#
#
# 07/01/06 10:00:08
set_working_dir E:/assignment/Verilog/task/test/news5f
set_working_dir E:/assignment/Verilog/task/assignment/spc
set register2register 50
set input2register 50
set r
music.map.rpt
Analysis & Synthesis report for music
Mon Jan 14 09:36:44 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal N
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity scan is
port(
clk_1000 : in vl_logic;
reset : in vl_logic;
input1 : in vl_logic_vect
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity binary_to_BCD is
port(
clk_i : in vl_logic;
rst_i : in vl_logic;
A : in vl_l