_primary.vhd

来自「复乘法器的FPGA实现」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity ADDSUB is
    port(
        add_sub         : in     vl_logic;
        dataa           : in     vl_logic_vector(15 downto 0);
        datab           : in     vl_logic_vector(15 downto 0);
        result          : out    vl_logic_vector(15 downto 0)
    );
end ADDSUB;