_primary.vhd

来自「一个电子中的verilog实验源代码。适合verilog初学者学习参考」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity scan is
    port(
        clk_1000        : in     vl_logic;
        reset           : in     vl_logic;
        input1          : in     vl_logic_vector(3 downto 0);
        input2          : in     vl_logic_vector(3 downto 0);
        input3          : in     vl_logic_vector(3 downto 0);
        input4          : in     vl_logic_vector(3 downto 0);
        input5          : in     vl_logic_vector(3 downto 0);
        input6          : in     vl_logic_vector(3 downto 0);
        led_scan        : out    vl_logic_vector(5 downto 0);
        led_bcd         : out    vl_logic_vector(3 downto 0)
    );
end scan;