_primary.vhd

来自「一个电子中的verilog实验源代码。适合verilog初学者学习参考」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity top is
    port(
        glbclk          : in     vl_logic;
        shift           : in     vl_logic;
        \select\        : in     vl_logic;
        set             : in     vl_logic;
        keyin           : in     vl_logic;
        led_scan        : out    vl_logic_vector(5 downto 0);
        led_out         : out    vl_logic_vector(7 downto 0);
        o_light         : out    vl_logic;
        alm_light       : out    vl_logic;
        reset           : out    vl_logic
    );
end top;