exemplar.his

Verilog HDL语言编写的5分频电路。采用两路时钟相逻辑作用产生。

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# 07/01/06 10:00:08
set_working_dir E:/assignment/Verilog/task/test/news5f
set_working_dir E:/assignment/Verilog/task/assignment/spc
set register2register 50
set input2register 50
set register2output 50
set input2output 50
_gc_read_init
_gc_run_init
set input_file_list { E:/assignment/Verilog/task/assignment/spc/spc.v }
set part 2s15cs144
set process 5
set wire_table xis215-5_avg
set chip TRUE
set macro FALSE
set area TRUE
set delay FALSE
set report brief
set hierarchy_auto TRUE
set hierarchy_preserve FALSE
set output_file E:/assignment/Verilog/task/test/news5f/spc.edf
set novendor_constraint_file FALSE
set target xis2
_gc_read
_gc_run
view_schematic -rtl -view