_primary.vhd

来自「一个电子中的verilog实验源代码。适合verilog初学者学习参考」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity binary_to_BCD is
    port(
        clk_i           : in     vl_logic;
        rst_i           : in     vl_logic;
        A               : in     vl_logic_vector(7 downto 0);
        ONES            : out    vl_logic_vector(3 downto 0);
        TENS            : out    vl_logic_vector(3 downto 0)
    );
end binary_to_BCD;