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Verilog 的代码
stop_watch.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fpga is
generic(
addr_bits : integer := 11;
data_bits : integer := 16;
col_bits : integer := 8;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity v51 is
port(
clk : in vl_logic;
data51 : out vl_logic_vector(7 downto 0);
ctl51 : ou
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity code_memory is
port(
address : in vl_logic_vector(15 downto 0);
code : out vl_logic_vector(31 downto 0)
240t.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
prev_cmp_uart_txd.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -
uart_txd.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -
graphics_pipeline.qsf.bak
# Copyright (C) 1991-2008 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
half_clk.qsf
# Copyright (C) 1991-2008 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity clk_contrl is
port(
clk_5m : in vl_logic;
rst : in vl_logic;
clk_2_5m : out vl_logi