_primary.vhd

关于乒乓操作的

library verilog;
use verilog.vl_types.all;
entity clk_contrl is
    port(
        clk_5m          : in     vl_logic;
        rst             : in     vl_logic;
        clk_2_5m        : out    vl_logic;
        clk_2_5m_inv    : out    vl_logic
    );
end clk_contrl;