prev_cmp_uart_txd.map.qmsg

基于verilog hdl的UART串口发送子程序。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 11 14:34:39 2009 " "Info: Processing started: Mon May 11 14:34:39 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off uart_txd -c uart_txd " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uart_txd -c uart_txd" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_txd.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file uart_txd.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_txd " "Info: Found entity 1: uart_txd" {  } { { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "uart_txd " "Info: Elaborating entity \"uart_txd\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_DIVIDE_BY_ZERO" "uart_txd.v(35) " "Warning (10216): Verilog HDL warning at uart_txd.v(35): expression attempts to divide or modulo by zero. Treated expression value as Don't Care (X) during synthesis." {  } { { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 35 0 0 } }  } 0 10216 "Verilog HDL warning at %1!s!: expression attempts to divide or modulo by zero. Treated expression value as Don't Care (X) during synthesis." 0 0 "" 0 -1}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "clk_baud 0 uart_txd.v(31) " "Warning (10030): Net \"clk_baud\" at uart_txd.v(31) has no driver or initial value, using a default initial value '0'" {  } { { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 31 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "" 0 -1}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "clk_out GND " "Warning (13410): Pin \"clk_out\" is stuck at GND" {  } { { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 20 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "TXD GND " "Warning (13410): Pin \"TXD\" is stuck at GND" {  } { { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 21 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "TI GND " "Warning (13410): Pin \"TI\" is stuck at GND" {  } { { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 22 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "10 " "Warning: Design contains 10 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "clk_in " "Warning (15610): No output dependent on input pin \"clk_in\"" {  } { { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 17 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "data_in\[0\] " "Warning (15610): No output dependent on input pin \"data_in\[0\]\"" {  } { { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 19 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "data_in\[1\] " "Warning (15610): No output dependent on input pin \"data_in\[1\]\"" {  } { { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 19 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "data_in\[2\] " "Warning (15610): No output dependent on input pin \"data_in\[2\]\"" {  } { { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 19 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "data_in\[3\] " "Warning (15610): No output dependent on input pin \"data_in\[3\]\"" {  } { { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 19 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "data_in\[4\] " "Warning (15610): No output dependent on input pin \"data_in\[4\]\"" {  } { { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 19 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "data_in\[5\] " "Warning (15610): No output dependent on input pin \"data_in\[5\]\"" {  } { { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 19 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "data_in\[6\] " "Warning (15610): No output dependent on input pin \"data_in\[6\]\"" {  } { { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 19 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "data_in\[7\] " "Warning (15610): No output dependent on input pin \"data_in\[7\]\"" {  } { { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 19 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "txd_en " "Warning (15610): No output dependent on input pin \"txd_en\"" {  } { { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 18 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "13 " "Info: Implemented 13 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "3 " "Info: Implemented 3 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 17 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "171 " "Info: Peak virtual memory: 171 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 11 14:34:44 2009 " "Info: Processing ended: Mon May 11 14:34:44 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}