240t.qsf

很好的一个东西,希望能对大家有所帮助.关于PWM的编程.

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		240t_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM2210GF324C3
set_global_assignment -name TOP_LEVEL_ENTITY 240t
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:11:41  DECEMBER 05, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION 7.2
set_global_assignment -name USER_LIBRARIES "E:/fpga/fpga_test_restored/db/"
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name BDF_FILE 240t.bdf
set_global_assignment -name VERILOG_FILE 240t.v
set_location_assignment PIN_J6 -to clk
set_global_assignment -name VERILOG_FILE leddrv.v
set_global_assignment -name VERILOG_FILE pwmon.v
set_global_assignment -name VERILOG_FILE uarts.v
set_global_assignment -name VERILOG_FILE uartr.v
set_global_assignment -name VERILOG_FILE sevenseg.v
set_global_assignment -name VERILOG_FILE pwm.v
set_global_assignment -name VERILOG_FILE civ.v
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_location_assignment PIN_V13 -to pwm
set_location_assignment PIN_V14 -to key_clk
set_location_assignment PIN_V5 -to led7
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_location_assignment PIN_V4 -to led6
set_location_assignment PIN_V12 -to led2