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Verilog 的代码
counter.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity idec is
port(
inst : in vl_logic_vector(11 downto 0);
aluasel : out vl_logic_vector(1 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity test_RISC_SPM is
generic(
word_size : integer := 16
);
end test_RISC_SPM;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity mux_h is
port(
i : in vl_logic_vector(2 downto 0);
h : out vl_logic_vector(7 downto 0)
);
e
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity add_12b is
port(
a : in vl_logic_vector(11 downto 0);
b : in vl_logic_vector(11 downto 0);
can_registers.prj
verilog work can_register_asyn_syn.v
verilog work can_register_asyn.v
verilog work can_register.v
verilog work can_registers.v
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity can_ibo is
port(
di : in vl_logic_vector(7 downto 0);
do : out vl_logic_vector(7 downto 0)
);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity plane_HV_precomputation is
port(
prev_in : in vl_logic_vector(14 downto 0);
A1 : in vl_logic_vector(7
intra_pred_pe.tlg
Selecting top level module Intra_pred_PE
@N:"E:\Verilog\H.264\Intra_pred_PE.v":1588:7:1588:8|Synthesizing module PE
@N:"E:\Verilog\H.264\Intra_pred_PE.v":18:7:18:19|Synthesizing module Intra_pred_
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity SL2 is
port(
a : in vl_logic_vector(31 downto 0);
y : out vl_logic_vector(31 downto 0)
);
e