_primary.vhd

用Verilog 编写的8位risc cpu

library verilog;
use verilog.vl_types.all;
entity idec is
    port(
        inst            : in     vl_logic_vector(11 downto 0);
        aluasel         : out    vl_logic_vector(1 downto 0);
        alubsel         : out    vl_logic_vector(1 downto 0);
        aluop           : out    vl_logic_vector(3 downto 0);
        wwe             : out    vl_logic;
        fwe             : out    vl_logic;
        zwe             : out    vl_logic;
        cwe             : out    vl_logic;
        bdpol           : out    vl_logic;
        option          : out    vl_logic;
        tris            : out    vl_logic
    );
end idec;