_primary.vhd

H.264标准解码器全部verilog源码

library verilog;
use verilog.vl_types.all;
entity plane_HV_precomputation is
    port(
        prev_in         : in     vl_logic_vector(14 downto 0);
        A1              : in     vl_logic_vector(7 downto 0);
        A2              : in     vl_logic_vector(7 downto 0);
        B1              : in     vl_logic_vector(7 downto 0);
        B2              : in     vl_logic_vector(7 downto 0);
        shifter1_len    : in     vl_logic_vector(1 downto 0);
        shifter2_len    : in     vl_logic_vector(1 downto 0);
        mux1_sel        : in     vl_logic;
        mux2_sel        : in     vl_logic;
        Is7             : in     vl_logic;
        HV_out          : out    vl_logic_vector(14 downto 0)
    );
end plane_HV_precomputation;