_primary.vhd

来自「fpga功能实现有限字长响应FIR 用verilog编写」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity add_12b is
    port(
        a               : in     vl_logic_vector(11 downto 0);
        b               : in     vl_logic_vector(11 downto 0);
        \out\           : out    vl_logic_vector(12 downto 0);
        co              : out    vl_logic
    );
end add_12b;